Tutorials by experts will provide review presentation of relevant topics.
Invited papers will introduce the mainstream topics.
Workshops organised in correlation with the ESREF conference will give the opportunity to exchange the know-how and field returns on specific topics.
NEW : "Case studies" workshop
The conference will be preceded by a half-day Tutorials on Tuesday, October 1st morning on the following topics:
Techniques and Approaches for Morphological Investigation on Dielectric Breakdown in High-k/Metal Stacks
by (Singapore University of Technology and Design, Singapore)
Nanoscopic physical analysis of breakdown in high-k gate/metal stacks shows that the microstructural defects and damages induced by dielectric breakdown in high-k gate dielectric are very different from that of conventional SiOxNy/poly-Si gate stacks. Chemical analysis using transmission electron microscopy (TEM) and electrical analysis using scanning tunnelling microscopy provide useful information about the nature and evolution of the breakdown induced defects and the roles of material microstructure responsible for dielectric breakdown in metal-oxide-semiconductor field effect transistors. Together with electrical characterization such as using Scanning Tunnelling Microscopy (STM), various microstructural and morphological changes at nanometer scale to the gate systems have been established. This tutorial will also report the latest TEM study on real-time high-k breakdown induced by an in-situ STM probe in TEM. The effect and role of breakdown induced microstructural changes on dielectric breakdown and recovery are identified. The impacts of the new breakdown and recovery mechanisms on the performance and reliability of high-k/metal gate stacks are discussed.
Directions for Failure Analysis in a Three-Dimensional World
by (Semitracks Corp., USA)
In addition to traditional scaling, the semiconductor industry now faces more significant challenges with vertical integration. Three-dimensional (3D) scaling and integration provides the major path forward. This vertical integration is occurring at all levels of the manufacturing process, from 3D transistors such as FinFETs, to 3D transistor integration, to 3D packaging. This push in the third dimension is introducing new failure mechanisms, but of more concern is the challenge associated with failure analysis. While there are some techniques that allow analysts to examine three-dimensional structures non-destructively, we do not have a robust set of techniques. This tutorial will discuss two topics: new failure mechanisms and new failure analysis techniques. In the first part of the tutorial, we will discuss some of the new failure mechanisms associated with 3D structures, both at the die level and the package level. In the second part of the tutorial, we will discuss how to isolate and characterize these new failure mechanisms. We will also more broadly discuss the challenges associated with analysis of 3D structures. We will discuss existing techniques, recently developed techniques, and what new techniques might be needed to provide increased chances of success on these complex circuits.
Reliability of embedding active and passive components in an interconnect substrate: disrupted supply chain logistics, yield management and limited rework and repair options
by (TechLead Corp., USA)
Embedding active and passive components in an interconnect substrate offers improved performance by cutting interconnect parasitics, reliability gains through elimination of wire-bonds and solder-bumps, and reduced cost and size via parts list reduction. Like every new development, these benefits come at a price: disrupted supply chain logistics, yield management complications and limited rework and repair options. Reliability considerations for embedded components include yield management strategies, WEEE and ROHS compliance, application specific life expectancy, and supply chain restructuring. The course also covers cost and warranty implications and concludes reviewing the drivers behind embedded active and passive components along with analysis of multiple examples of today’s real life embedded component applications.
Invited papers will introduce the mainstream topics. A confirmed list of invited papers follows:
UTBB FD-SOI Technology : an Optimum Tradeoff on Energy Efficiency and Resilience
by (ST Microelectronics – France)
UTBB FD-SOI technology has become mainstream within STMicroelectronics, with the objective to serve a wide spectrum of multimedia products. This breakthrough technology brings significant improvements in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. The symbiosis between process, design and reliability was key in this achievement. It enables to provide already at 28nm node a real differentiation by offering the best trade-off between performance and power while being both cost-effective with respect to any process available on the market.
Moving from bulk to UTBB FD-SOI offers new perspectives towards product hardening and qualification. The electrical reliability challenges related to UTBB FD-SOI in the multicore era will be addressed. Then, it will be highlighted how the designers together with process engineers have deployed a unique UTBB FD-SOI/BULK hybrid strategy to reach the industrial ESD standards. Finally, the enhanced radiation hardness with FDSOI28 technology will be presented as an opportunity to leverage existing rad-hard design solutions for an extended differentiation in the SER field.
Long-term ElectroMagnetic Robustness of Integrated Circuits: EMRIC research project
by (LAAS-CNRS,Université de Toulouse, France)
Introducing new high performance electronic modules in automotive, aeronautic and aerospace applications forces system manufacturers to optimize system reliability and reduce time to market delivery and manufacturing costs. This trend has triggered off an increasing demand for conclusive statements about future lifetime and function of the product already at the design stage, ranging from electromagnetic effects (EMC/RF) to thermal management issues and thermo-mechanical reliability forecasts. Ensuring the electromagnetic robustness of nanoscale integrated circuits (extension of the electromagnetic compatibility for the full lifetime of the product) has become a key challenge. During their lifetime, integrated circuits may be affected by failure mechanisms mainly activated by harsh environmental conditions. Even if failure mechanisms do not compromise the circuit operation, IC intrinsic degradations can have a significant impact on EMC performances. EMRIC project was developed to study, evaluate and predict the impact of circuit aging on IC electromagnetic behavior. The aim of this presentation is to clarify the aging impact on emission and immunity level of various analog and digital integrated circuits, evaluate the effect of design options, correlate degradation mechanisms with EMC drifts and predict EMC behavior after years of use.
Effectiveness of the scanning nonlinear dielectric microscopy on the failure analysis of semiconductor devices
by (Tohoku University, Sendai - Japan)
Recently, the scanning nonlinear dielectric microscopy (SNDM) has attracted considerable attention for use in semiconductor device analysis owing to its high sensitivity to capacitance variation, on the order of 10-22 F. Previously, we reported the detection of two-dimensional dopant profile in a transistor and the failure analysis of a load transistor in a static random access memory device. We also used SNDM to reveal the detailed distribution of accumulated charges in the SiO2-SiN-SiO2 (ONO) layer of a cell transistor in a metal-ONO-semiconductor (MONOS) memory. SNDM can also image the charge in the floating gate of a floating-gate-type flash memory.
We will introduce an advanced SNDM method, under an applied dc bias voltage, for high resolution imaging of accumulated charges, and observation of the threshold voltage (Vth) distribution of the cell transistors in a MONOS flash memory. We will demonstrate that this method is effective in the failure and reliability analysis of semiconductor devices.
We could obtain the high-resolution image of accumulated charges by detecting the higher-order (2-4 order) nonlinear permittivity. The obtained image contrast can be interpreted using a higher-order differential coefficient (dnC/dVn) of a quasi-static C-V curve of the ONO-Si interface capacitance as a function of externally applied dc-voltage. By using a higher-order nonlinear image, the charge concentration resolution can be improved. By detecting a dc-biased lowest order nonlinear permittivity (conventional SNDM signal), the Vth distribution of the cell transistors was obtained; together with information on charge redistribution associated with program disturb failure.
Based on the results obtained in these studies, it is expected that SNDM will be an effective technique for analyzing the reliability of semiconductor devices.
Qualification of 50V GaN on SiC technology for RF Power amplifiers
by (NXP Semiconductors – The Netherlands, *United Monolithic Semiconductors - France, Germany, **Fraunhofer Institute for Applied Solid State Physics (IAF)
This paper describes the qualification of the 50V, 0.5m GaN on SiC process that has been released at the III-V fab of UMS in Ulm in cooperation with IAF and NXP Semiconductors. The qualification at NXP is split into two parts: part 1: investigation of die related wear-out failure mechanisms using a power device with 7.2mm gate width and part 2: final process release using the first product of NXP, a 50W wide band amplifier. The aim of the first part is to determine the acceleration factors for the major electric failure mechanism. These will be then used to define the qualification program of the wide band amplifier which will also include all package related tests. In this paper we will show how the tests are defined using the mission profile of the product. In addition, we will show the results. They are compared to results published in literature and are shown to be very promising.
High optical strength GaAs-based laser structures
by (3S PHOTONICS – France)
The optical-strength properties of our GaAs-based semiconductor laser structures are presented. After some general considerations about this robustness issue, typical of high-power diode lasers, the performances in both CW and pulsed current injection of our best vertical structures are presented and it is shown that our current generation of 980nm laser diodes can withstand very high facet temperatures (180-200°C) in stable CW operation. Thus, we are able to demonstrate a large margin between the facet temperature in operation conditions and the observed maximum critical value. Maximum CW saturation powers exceeding 3W from a single-lateral mode device have been with some obtained with the longest laser cavities (7.5mm) at around 5 Amps. Also, very high peak powers are demonstrated in pulsed current experiments opening the way to new specific applications, using available production devices. Specific degradation patterns after high peak current single-pulse damage have been observed by cathodo-luminescence imaging and will also be discussed, together additional failure analysis results. Finally, comparisons between devices emitting at 980nm and 1060nm are also considered.
Application of advanced process control, reliability and failure analysis methods for Fan-Out WLP Technology eWLB
by (Nanium SA – Portugal)
Faster product learning cycles play a key role on business competitiveness. Due to current market needs mainly in the wireless and mobile communications applications, product lifetime is getting shorter and shorter, leaving less time to deeply analyze and fix technology or process related failure mechanisms, which show up in high volume production and have not been detected during the development phase already. Working on the semiconductor packaging and test industry and aiming on this objective, NANIUM has been developing and using several techniques that allow a faster response to problem characterization and reliability assessment on eWLB products. This paper will brief on the experience acquired over the last 2 years by sharing the relevant application cases of failure analysis, reliability stress methods and process control enhancement.
MEMS packaging reliability assessment Residual Gas Analysis of gaseous species trapped inside MEMS cavity
by (CEA, LETI – France)
The reliability of MEMS sensors or actuators such as accelerometers, gyroscopes, resonators, RF switches, microbolometers… is critically dependent on the vacuum level and on the nature of the gaseous species present inside the MEMS cavity (~1mm3 or less, usually in the 10-2-10-3 mbar vacuum range after sealing by Wafer Level Packaging process). Although a lot of methods have been explored, the Residual Gas Analysis (RGA) method -however destructive- reveals to be an interesting method to determine the possible sources of gaseous species present in the MEMS cavity, in order to assess to which extent a given packaging technology is capable of maintaining the required environmental conditions all along the device lifetime.
This paper introduces results recently achieved with a specific RGA test bench developed at CEA-LETI to meet these requirements. This Ultra High Vacuum (UHV) RGA equipment operates with a residual background pressure level in the 10-10 mbar range and uses a quadrupolar mass spectrometer (QMS) for gas analysis.
Experimental results confirm that the RGA technique may be successfully used to identify the nature and proportions of gases trapped in cavities as small as 1 mm3 under a residual pressure lower than 10-2 mbar.
Trends in automotive power semiconductor packaging
by (Fuji Electric Europe GmbH – Germany)
In the past the main focus for improvements of power electronic modules was set on the chip technology. Therefore, looking on the cross section structure of modern modules, only small steps of improvements were done in the last decades. Reason for that is that the construction and joining technology satisfy the market requirements. Furthermore the power electronic market segment is smaller than the one of microelectronic devices. Therefore it had to use their production facilities like e.g. bond wire machines.
In the future this will change because of the following reasons:
Power electronic performance depends by a high ratio on package technology.
The automotive industry has high requirements regarding cost efficiency, reliability and compactness. Furthermore they have big lever for innovations to make a product fit this requirement. Power electronic devices are used in (H)EVs.
The chips in future will require new package technologies. This presentation will explain the need of this paradigm shift, give an overview of the new technologies and will present Fuji’s package solution proposals.
Thin film silicon photovoltaics from glass substrates to flexible organic/plastic substrates
by (ST Microelectronics also with 3SUN s.r.l – Italy)
Thin-film solar cells have made great progress during the past decade and have stimulated great research and commercial interest. In this work we will discuss about factors governing the manufacturing of thin-film silicon modules that are determined by technological reasons as well as by economic considerations. During the past year the fast decrease of crystalline silicon solar cells prices has made thin film silicon technology more challenging than before. To survive in the tough competitive environment thin film silicon large area module efficiency has to be raised from the current ~ 10% to more than 13% in the next few years with even more competitive costs. We will discuss on the activities aimed at increasing the efficiency, reducing the manufacturing costs and ensuring long term reliability.
Furthermore, it is paramount to quickly develop all the potential advantages that can make thin film more competitive than silicon wafer technology such as lightweight, high throughput manufacturing, suitability for building integrated PV and manufacturability on flexible organic/plastic substrates. In particular, the realization of flexible solar cells is also interesting for new applications such as indoor energy harvesting for sensors or other smart electronic systems that will be discussed in this work.
will be moderated by Olivier Crepel (EADS - France) and Philippe Perdu (CNES - France) on Thursday, October 3rd, afternoon.
This workshop will be focused on :
will be organized by Richard Langford (University of Cambridge - UK) on Monday September 30th.
For further information, please visit: www.imec.be/efug/.
will be organised by Golta Khatibi - Faculty of Physics, University of Vienna and by and Infineon Technologies AG on Tuesday, October 1, 16:40-18:30
In the recent years manufactures of electronic products are seeking for efficient and reliable accelerated testing methods to keep up with market demands. At present, accelerated power and temperature cycling tests count as the state of the art for reliability assessment of microelectronic devices. Decreasing the time to failure is commonly achieved by increasing the temperature swing or reduction the duration of testing which may results in occurrence of damage mechanisms other than those encountered in real application or suppressing these failures.
In this study a novel concept for qualification of microelectronic devices as a cost and time saving alternative to the conventional testing procedures is presented. The principle idea of this approach is replacement of thermally induced strains by means of equivalent mechanical strains. Using accelerated mechanical fatigue set-ups, the test structures can be subjected to single and multi-axial cyclic loading at high testing frequencies and lifetime curves can be obtained. Following a physics of failure approach, the suggested procedures enable detection of the weak sites of the devices in a very short duration of time. Application of Finite Element Analysis allows establishment of lifetime prediction models. Exemplary results demonstrate the applicability of the proposed method for qualification of interconnects in power semiconductors.
The workshop includes the following topics:
will be organized by Philippe Perdu (CNES - France) on Wednesday October 2nd 18:00-20:00.
The topic of this EUFANET workshop is Sample prep challenges and solutions
Sample prep is getting one of the most challenging part of a failure analysis. It starts with chip access challenges: SiP, power, stacked dies and other 3D devices, repackaging, package opening, silicon thinning and polishing, specific challenges for SIL (flatness, roughness) and for no Si devices (GaN, SiC...).
When a defect is roughly localized, the sample prep plays again a key role: cross section or delayering? Vertical, horizontal or transversal TEM lamellas... Sample prep for atom probe and other specific analysis (Auger...)
More info on EUFANET at www.eufanet.org.
This edition will focus on Reliability of Passive and SiC Devices.